A Self-Repairing Digital System with High-Quality Scalability and Fault Coverage

S. Ravichand, T. Madhu, M. Sailaja

Abstract


In any fault tolerant or BIST system the primary goal is to covenant with faults that arise in the indented system. The proposed system using genetic algorithm to optimize the performance and area of given circuit.  This approach is supple for combinational circuit design. The use of four spare cells simplifies the operation of the active block in the current system; it needs more space to establish itself so it is considered as overhead. The proposed method of fault detection and correction for logical errors using genetic algorithm decreases the area overhead. Detection of Fault in the memory unit through BIST implementation increases the speed but replacing the existing faulty block with fault free block degrades the fault analyzing capabilities. Utmost care has on all the works implemented for the process of minimizing the error in different digital process. Therefore, with the new scope of proposing the method of reducing the error flow for the application of medical field, aeronautical, satellite broadcasting is described very efficiently in this paper. The simulation results of the fault tolerant and self-repairing method using genetic algorithm is presented.

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DOI: https://doi.org/10.23956/ijermt.v6i8.145

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